module HC_FPGA_Demo_Top
(
    input CLOCK_XTAL_50MHz,
	input RESET,
    input  RXD,
    output TXD,
    output LED0,
    output LED1,
    output LED2,
    output LED3,
	output[7:0] DIG,
	output[5:0] SEL
);



my_jsq u_jsq
(
    .clk(CLOCK_XTAL_50MHz),
    .rst_n(RESET),
    .led(LED1)
);


endmodule
